Accurate microarchitecture-level fault modeling for studying hardware faults

Man Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault tolerance mechanisms across all levels of the system stack, from the device level to the system level. High-level fault tolerance solutions, such as at the microarchitecture and system levels, are commonly evaluated using statistical fault injections with microarchitecture-level fault models. Since hardware faults actually manifest at a much lower level, it is unclear if such high level fault models are acceptably accurate. On the other hand, lower level models, such as at the gate level, may be more accurate, but their increased simulation times make it hard to track the system-level propagation of faults. Thus, an evaluation of high-level reliability solutions entails the classical tradeoff between speed and accuracy. This paper seeks to quantify and alleviate this tradeoff. We make the following contributions: (1) We introduce SWAT-Sim, a novel fault injection infrastructure that uses hierarchical simulation to study the system-level manifestations of permanent (and transient) gate-level faults. For our experiments, SWAT-Sim incurs a small average performance overhead of under 3x, for the components we simulate, when compared to pure microarchitectural simulations. (2) We study system-level manifestations of faults injected under different microarchitecture-level and gate-level fault models and identify the reasons for the inability of microarchitecture-level faults to model gate-level faults in general. (3) Based on our analysis, we derive two probabilistic microarchitecture-level fault models to mimic gate-level stuck-at and delay faults. Our results show that these models are, in general, inaccurate as they do not capture the complex manifestation of gate-level faults. The inaccuracies in existing models and the lack of more accurate microarchitecturelevel models motivate using infrastructures similar to SWATSim to faithfully model the microarchitecture-level effects of gate-level faults.

Original languageEnglish (US)
Title of host publicationProceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009
Pages105-116
Number of pages12
DOIs
StatePublished - Apr 24 2009
Event2008 IEEE International Conference on Mechatronics and Automation, ICMA 2008 - Takamatsu, Japan
Duration: Aug 5 2008Aug 8 2008

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other2008 IEEE International Conference on Mechatronics and Automation, ICMA 2008
CountryJapan
CityTakamatsu
Period8/5/088/8/08

ASJC Scopus subject areas

  • Hardware and Architecture

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  • Cite this

    Li, M. L., Ramachandran, P., Karpuzcu, U. R., Hari, S. K. S., & Adve, S. V. (2009). Accurate microarchitecture-level fault modeling for studying hardware faults. In Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009 (pp. 105-116). [4798242] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2009.4798242