Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration

Wei Zuo, Louis Noel Pouchet, Andrey Ayupov, Taemin Kim, Chung Wei Lin, Shinichi Shiraishi, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A desirable feature of a development tool for SoC design is that, given the important applications in the domain to be targeted by the SoC, a powerful hardware-software partitioning engine is available to determine which function(s) shall be mapped to hardware. However, to provide high-quality partitioning, this engine must be able to consider a rich design space of possible alternate hardware and software implementations for each program region candidate for hardware acceleration, in turn making the task of finding the optimal mapping very difficult given the number of design points to consider and the need for accurate modeling of latency, power and area. In this work we propose a novel framework to enable hardware acceleration of performance-critical parts of an application, by addressing the problem of hardware/software partitioning under power and area constraints to minimize the overall program latency. Our flow is based on the LLVM compiler, and focuses on building a scalable compile-Time partitioning algorithm while considering large sets of alternative hardware and software implementations for a particular region. To this end we develop a hybrid approach based on mixing semi-random selection of hardware design points and an Integer Linear Programming formulation of the mapping decision, along with iterative refinements of the solution. Experimental results demonstrate the capability of our approach to consider complex designs and yet output near-optimal partitioning decision. Our package is named RIP (Randomized ILP-based Partitioning), and is open source to benefit the research community.

Original languageEnglish (US)
Title of host publicationProceedings of the 54th Annual Design Automation Conference 2017, DAC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450349277
DOIs
StatePublished - Jun 18 2017
Event54th Annual Design Automation Conference, DAC 2017 - Austin, United States
Duration: Jun 18 2017Jun 22 2017

Publication series

NameProceedings - Design Automation Conference
VolumePart 128280
ISSN (Print)0738-100X

Other

Other54th Annual Design Automation Conference, DAC 2017
CountryUnited States
CityAustin
Period6/18/176/22/17

Fingerprint

Hardware/software Co-design
Design Space Exploration
Partitioning
Hardware/software Partitioning
Hardware Acceleration
Hardware
Modeling
Latency
Engine
Iterative Refinement
Software
Hardware Design
Integer Linear Programming
Hybrid Approach
Large Set
Open Source
Compiler
Alternate
Engines
Minimise

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Zuo, W., Pouchet, L. N., Ayupov, A., Kim, T., Lin, C. W., Shiraishi, S., & Chen, D. (2017). Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration. In Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017 [78] (Proceedings - Design Automation Conference; Vol. Part 128280). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3061639.3062195

Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration. / Zuo, Wei; Pouchet, Louis Noel; Ayupov, Andrey; Kim, Taemin; Lin, Chung Wei; Shiraishi, Shinichi; Chen, Deming.

Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 78 (Proceedings - Design Automation Conference; Vol. Part 128280).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zuo, W, Pouchet, LN, Ayupov, A, Kim, T, Lin, CW, Shiraishi, S & Chen, D 2017, Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration. in Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017., 78, Proceedings - Design Automation Conference, vol. Part 128280, Institute of Electrical and Electronics Engineers Inc., 54th Annual Design Automation Conference, DAC 2017, Austin, United States, 6/18/17. https://doi.org/10.1145/3061639.3062195
Zuo W, Pouchet LN, Ayupov A, Kim T, Lin CW, Shiraishi S et al. Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration. In Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 78. (Proceedings - Design Automation Conference). https://doi.org/10.1145/3061639.3062195
Zuo, Wei ; Pouchet, Louis Noel ; Ayupov, Andrey ; Kim, Taemin ; Lin, Chung Wei ; Shiraishi, Shinichi ; Chen, Deming. / Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration. Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings - Design Automation Conference).
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