Accelerating sparse deep neural networks on FPGAs

Sitao Huang, Carl Pearson, Rakesh Nagi, Jinjun Xiong, Deming Chen, Wen Mei Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Deep neural networks (DNNs) have been widely adopted in many domains, including computer vision, natural language processing, and medical care. Recent research reveals that sparsity in DNN parameters can be exploited to reduce inference computational complexity and improve network quality. However, sparsity also introduces irregularity and extra complexity in data processing, which make the accelerator design challenging. This work presents the design and implementation of a highly flexible sparse DNN inference accelerator on FPGA. Our proposed inference engine can be easily configured to be used in both mobile computing and high-performance computing scenarios. Evaluation shows our proposed inference engine effectively accelerates sparse DNNs and outperforms CPU solution by up to 4.7 \times in terms of energy efficiency.

Original languageEnglish (US)
Title of host publication2019 IEEE High Performance Extreme Computing Conference, HPEC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728150208
DOIs
StatePublished - Sep 2019
Event2019 IEEE High Performance Extreme Computing Conference, HPEC 2019 - Waltham, United States
Duration: Sep 24 2019Sep 26 2019

Publication series

Name2019 IEEE High Performance Extreme Computing Conference, HPEC 2019

Conference

Conference2019 IEEE High Performance Extreme Computing Conference, HPEC 2019
CountryUnited States
CityWaltham
Period9/24/199/26/19

Keywords

  • Deep learning
  • FPGA
  • Graphs
  • Sparse DNN

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Artificial Intelligence

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  • Cite this

    Huang, S., Pearson, C., Nagi, R., Xiong, J., Chen, D., & Hwu, W. M. (2019). Accelerating sparse deep neural networks on FPGAs. In 2019 IEEE High Performance Extreme Computing Conference, HPEC 2019 [8916419] (2019 IEEE High Performance Extreme Computing Conference, HPEC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HPEC.2019.8916419