Accelerating data movement on future chip multi-processors

Junli Gu, Rakesh Kumar, Steven Sam Lumetta, Yihe Sun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Moving data between cores on hardware coherent architectures suffers from memory latency and causes cache misses and coherence traffic, which are obstacles to achieving high performance. In this paper, we evaluate the potential for hardware optimization of message data transfer on chip multiprocessors with a combination of NAS parallel MPI benchmarks, Intel IMB MPI benchmarks, and a few microbenchmarks on a full-system simulator based on Simics and FeS2. We show that while passive hardware driven by cores can reduce cache traffic, it provides limited performance gains. We propose a data movement manager (DMM) that uses the on-chip coherence protocols to implement zero-copy message passing between separate address spaces and to remove synchronization and copy overheads from the processors. We also discuss methods for managing data placement in caches to reduce latency. We show that such a design shows substantial promise for both cache traffic reduction and performance improvements.

Original languageEnglish (US)
Title of host publicationProceedings of the 2nd International Forum on Next-Generation Multicore/Manycore Technologies, IFMT'2010 - In Conjunction with the 37th Intl. Symposium on Computer Architecture, ISCA 2010
DOIs
StatePublished - Dec 1 2010
Event2nd International Forum on Next Generation Multicore/Manycore Technologies, IFMT'2010, Co-located with the 37th International Symposium on Computer Architecture, ISCA 2010 - Saint-Malo, France
Duration: Jun 19 2010Jun 19 2010

Publication series

NameACM International Conference Proceeding Series

Other

Other2nd International Forum on Next Generation Multicore/Manycore Technologies, IFMT'2010, Co-located with the 37th International Symposium on Computer Architecture, ISCA 2010
CountryFrance
CitySaint-Malo
Period6/19/106/19/10

Keywords

  • cache hierarchy
  • data movement
  • memory hierarchy
  • multi-core
  • multi-core architecture design

ASJC Scopus subject areas

  • Software
  • Human-Computer Interaction
  • Computer Vision and Pattern Recognition
  • Computer Networks and Communications

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