Accelerating data movement on future chip multi-processors

Moving data between cores on hardware coherent architectures suffers from memory latency and causes cache misses and coherence traffic, which are obstacles to achieving high performance. In this paper, we evaluate the potential for hardware optimization of message data transfer on chip multiprocessors with a combination of NAS parallel MPI benchmarks, Intel IMB MPI benchmarks, and a few microbenchmarks on a full-system simulator based on Simics and FeS2. We show that while passive hardware driven by cores can reduce cache traffic, it provides limited performance gains. We propose a data movement manager (DMM) that uses the on-chip coherence protocols to implement zero-copy message passing between separate address spaces and to remove synchronization and copy overheads from the processors. We also discuss methods for managing data placement in caches to reduce latency. We show that such a design shows substantial promise for both cache traffic reduction and performance improvements.