Abstract
This paper presents a generic approach of exploiting GPU parallelism to speed up the essential computations in VLSI nonlinear analytical placement. We consider the computation of wirelength and density which are widely used as cost and constraint in nonlinear analytical placement. For wirelength gradient computing, we utilize the sparse characteristic of circuit graph to transform the compute-intensive portions into sparse matrix multiplications, which effectively optimizes the memory access pattern and mitigates the imbalance workload. For density, we introduce a computation flattening technique to achieve load balancing among threads and a High-Precision representation is integrated into our approach to guarantee the reproducibility. We have evaluated our method on a set of contest benchmarks from industry. The experimental results demonstrate our GPU method achieves a better performance over both the CPU methods and the straightforward GPU implementation.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1345-1350 |
| Number of pages | 6 |
| ISBN (Electronic) | 9783981926316 |
| DOIs | |
| State | Published - Apr 19 2018 |
| Event | 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany Duration: Mar 19 2018 → Mar 23 2018 |
Publication series
| Name | Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
|---|---|
| Volume | 2018-January |
Other
| Other | 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
|---|---|
| Country | Germany |
| City | Dresden |
| Period | 3/19/18 → 3/23/18 |
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ASJC Scopus subject areas
- Safety, Risk, Reliability and Quality
- Hardware and Architecture
- Software
- Information Systems and Management
Cite this
Accelerate analytical placement with GPU : A generic approach. / Lin, Chun Xun; Wong, Martin D F.
Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1345-1350 (Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018; Vol. 2018-January).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Accelerate analytical placement with GPU
T2 - A generic approach
AU - Lin, Chun Xun
AU - Wong, Martin D F
PY - 2018/4/19
Y1 - 2018/4/19
N2 - This paper presents a generic approach of exploiting GPU parallelism to speed up the essential computations in VLSI nonlinear analytical placement. We consider the computation of wirelength and density which are widely used as cost and constraint in nonlinear analytical placement. For wirelength gradient computing, we utilize the sparse characteristic of circuit graph to transform the compute-intensive portions into sparse matrix multiplications, which effectively optimizes the memory access pattern and mitigates the imbalance workload. For density, we introduce a computation flattening technique to achieve load balancing among threads and a High-Precision representation is integrated into our approach to guarantee the reproducibility. We have evaluated our method on a set of contest benchmarks from industry. The experimental results demonstrate our GPU method achieves a better performance over both the CPU methods and the straightforward GPU implementation.
AB - This paper presents a generic approach of exploiting GPU parallelism to speed up the essential computations in VLSI nonlinear analytical placement. We consider the computation of wirelength and density which are widely used as cost and constraint in nonlinear analytical placement. For wirelength gradient computing, we utilize the sparse characteristic of circuit graph to transform the compute-intensive portions into sparse matrix multiplications, which effectively optimizes the memory access pattern and mitigates the imbalance workload. For density, we introduce a computation flattening technique to achieve load balancing among threads and a High-Precision representation is integrated into our approach to guarantee the reproducibility. We have evaluated our method on a set of contest benchmarks from industry. The experimental results demonstrate our GPU method achieves a better performance over both the CPU methods and the straightforward GPU implementation.
UR - http://www.scopus.com/inward/record.url?scp=85048783823&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048783823&partnerID=8YFLogxK
U2 - 10.23919/DATE.2018.8342222
DO - 10.23919/DATE.2018.8342222
M3 - Conference contribution
AN - SCOPUS:85048783823
T3 - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
SP - 1345
EP - 1350
BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -