A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS

Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert Pilawa-Podgurski, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multi-phase switching DC-DC converters offer many advantages in terms of high output power, low ripple, fast load transient response, high efficiency across a very wide range of load currents, and alleviated output filter requirements. However, the need for complex controllers that ensure accurate regulation and uniform current sharing between phases along with generation of multiple matched pulse-width modulated (PWM) signals complicate the design of multi-phase converters. Hysteretic control offers the simplest means to implement multi-phase converters and has been widely used in the prior art [1]. However, its nonlinear behavior leads to large output ripple, unpredictable loop dynamics, and wide variation in switching frequency (Fsw), which are undesirable in many noise-sensitive applications. Furthermore, they require current sensors to implement active current sharing, and generation of multiple synchronized PWM signals requires power hungry circuits [1]. A voltage-mode controller using a type-Ill compensator is well-suited for low-noise applications but it requires multiple synchronized and matched ramp generators that also incur large area and power penalty. A digital PWM generator can provide accurately matched multi-phase PWM signals thereby enabling passive current sharing, but digitally controlled buck converters exhibit large ripple due to their limit cycle behavior, have poor transient response, and consume significant quiescent current [2][3]. All these issues become even more challenging to address in high-Fsw converters because of more stringent loop-delay requirements.

Original languageEnglish (US)
Title of host publication2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages216-217
Number of pages2
ISBN (Electronic)9781479962235
DOIs
StatePublished - Mar 17 2015
Event2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States
Duration: Feb 22 2015Feb 26 2015

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume58
ISSN (Print)0193-6530

Other

Other2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
CountryUnited States
CitySan Francisco
Period2/22/152/26/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Kim, S. J., Nandwana, R. K., Khan, Q., Pilawa-Podgurski, R., & Hanumolu, P. K. (2015). A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers (pp. 216-217). [7063003] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2015.7063003