TY - GEN
T1 - A wide tracking range 0.2-4Gbps clock and data recovery circuit
AU - Hanumolu, Pavan Kumar
AU - Wei, Gu Yeon
AU - Moon, Un Ku
PY - 2006
Y1 - 2006
N2 - A hybrid analog and digital quarter-rate clock and data recovery circuit employs a second-order digital loop filter with delta-sigma truncation to achieve sub-ps phase resolution and better than 2ppm frequency resolution. A test chip fabricated in a 0.18μm CMOS process achieves BER < 10 -12 and consumes 14mW power while operating at 2Gbps. The tracking range is greater than ±5000ppm and ±2500 ppm at 10kHz and 20kHz modulation frequencies respectively, thus, making this CDR suitable for systems with spread spectrum clocking.
AB - A hybrid analog and digital quarter-rate clock and data recovery circuit employs a second-order digital loop filter with delta-sigma truncation to achieve sub-ps phase resolution and better than 2ppm frequency resolution. A test chip fabricated in a 0.18μm CMOS process achieves BER < 10 -12 and consumes 14mW power while operating at 2Gbps. The tracking range is greater than ±5000ppm and ±2500 ppm at 10kHz and 20kHz modulation frequencies respectively, thus, making this CDR suitable for systems with spread spectrum clocking.
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M3 - Conference contribution
AN - SCOPUS:39749151119
SN - 1424400066
SN - 9781424400065
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 71
EP - 72
BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
T2 - 2006 Symposium on VLSI Circuits, VLSIC
Y2 - 15 June 2006 through 17 June 2006
ER -