A voltage overscaled low-power digital filter IC

Rajamohana Hegde; Naresh R. Shanbhag

doi:10.1109/JSSC.2003.821775

A voltage overscaled low-power digital filter IC

Research output: Contribution to journal › Article › peer-review

Abstract

In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-μm 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05 f_s-0.25 f_s, where f_s is the sampling frequency).

Original language	English (US)
Pages (from-to)	388-391
Number of pages	4
Journal	IEEE Journal of Solid-State Circuits
Volume	39
Issue number	2
DOIs	https://doi.org/10.1109/JSSC.2003.821775
State	Published - Feb 2004

Keywords

Error control
Low power
Voltage overscaling

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/JSSC.2003.821775

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abstract = "In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-μm 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05 fs-0.25 fs, where fs is the sampling frequency).",

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note = "Funding Information: Manuscript received November 19, 2002; revised October 6, 2003. This work was supported by the National Science Foundation under Grant CCR 00-00987. R. Hegde is with Intersymbol Communications Inc., Champaign, IL 61821 USA (e-mail: raj@intersymbol.com). N. R. Shanbhag is with the Electrical and Computer Engineering Department and Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA (e-mail: shanbhag@mail.icims.csl.uiuc.edu). Digital Object Identifier 10.1109/JSSC.2003.821775",

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AU - Shanbhag, Naresh R.

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N2 - In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-μm 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05 fs-0.25 fs, where fs is the sampling frequency).

AB - In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-μm 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05 fs-0.25 fs, where fs is the sampling frequency).

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A voltage overscaled low-power digital filter IC

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