A voltage overscaled low-power digital filter IC

Rajamohana Hegde, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review


In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-μm 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05 fs-0.25 fs, where fs is the sampling frequency).

Original languageEnglish (US)
Pages (from-to)388-391
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Issue number2
StatePublished - Feb 2004


  • Error control
  • Low power
  • Voltage overscaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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