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A Verilog-A compact model for ESD protection NMOSTs
Junjun Li
, Sopan Joshi
,
Elyse Rosenbaum
Electrical and Computer Engineering
Coordinated Science Lab
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Keyphrases
Compact Model
100%
Verilog
100%
ESD Protection
100%
Convergence Problem
50%
Small Signal
50%
Model-driven Development
50%
Circuit-level Simulation
50%
Transient Simulation
50%
Large-signal Model
50%
Avalanche multiplication Factor
50%
Engineering
Transients
100%
Signal Model
100%
Convergence Problem
100%
Avalanche Multiplication
100%
Multiplication Factor
100%
Computer Science
Verilog
100%
Level Simulation
50%
Model Development
50%
Mathematics
Convergence Problem
100%
Material Science
Electronic Circuit
100%