Abstract

This paper describes die development of a variance minimization strategy for the tolerancing of linear circuits and systems. The technique is conceptually simple and can be implemented through commonly available optimization routines. The applicability of the approach is illustrated through standard numerical examples. In addition the paper also derives a new expression for the variance of a system performance index.

Original languageEnglish (US)
Pages (from-to)737-747
Number of pages11
JournalIEEE Transactions on Circuits and Systems
Volume27
Issue number9
DOIs
StatePublished - Sep 1980

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Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

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A Variance Minimization Approach to Tolerance Design. / Iyer, Ravishankar Krishnan; Downs, Thomas.

In: IEEE Transactions on Circuits and Systems, Vol. 27, No. 9, 09.1980, p. 737-747.

Research output: Contribution to journalArticle

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