TY - JOUR
T1 - A Unified Formalization of Four Shared-Memory Models
AU - Adve, Sarita V.
AU - Hill, Mark D.
N1 - Funding Information:
Manuscript received September 7, 1990; revised August 1, 1992. This work was supported in part by a National Science Foundation Presidential Young Investigator Award (MIPS-8957278) with matching funds from A. T.&T. Bell Laboratories, Cray Research Foundation, and Digital Equipment Corporation. S. Adve was also supported by an IBM graduate fellowship.
PY - 1993/6
Y1 - 1993/6
N2 - This paper presents a shared-memory model, data- race-free-1, that unifies four earlier models: weak ordering, re-lease consistency (with sequentially consistent special operations), the VAX memory model, and data-race-free-O. The most intuitive and commonly assumed shared-memory model, sequential consistency, limits performance. The models of weak ordering, release consistency, the VAX, and data-race-free-0 are based on the common intuition that if programs synchronize explicitly and correctly, then sequential consistency can be guaranteed with high performance. However, each model formalizes this intuition differently and has different advantages and disadvantages with respect to the other models. Data-race-free-1 unifies the models of weak ordering, release consistency, the VAX, and data-race-free-0 by formalizing the above intuition in a manner that retains the advantages of each of the four models. A multiprocessor is data-race-free-1 if it guarantees sequential consistency to data-race-free programs. Data-race-free-1 unifies the four models by providing a programmer’s interface similar to the four models, and by allowing all implementations allowed by the four models. Additionally, data-race-free-1 expresses the programmer’s interface more explicitly and formally than weak ordering and the VAX, and allows an implementation not allowed by weak ordering, release consistency, or data-race-free-0, The new implementation proposal for data-race-free-1 differs from earlier implementations mainly by permitting the execution of all synchronization operations of a processor even while previous data operations of the processor are in progress. To ensure sequential consistency, two synchronizing processors exchange information to delay later operations of the second processor that conflict with an incomplete data operation of the first processor.
AB - This paper presents a shared-memory model, data- race-free-1, that unifies four earlier models: weak ordering, re-lease consistency (with sequentially consistent special operations), the VAX memory model, and data-race-free-O. The most intuitive and commonly assumed shared-memory model, sequential consistency, limits performance. The models of weak ordering, release consistency, the VAX, and data-race-free-0 are based on the common intuition that if programs synchronize explicitly and correctly, then sequential consistency can be guaranteed with high performance. However, each model formalizes this intuition differently and has different advantages and disadvantages with respect to the other models. Data-race-free-1 unifies the models of weak ordering, release consistency, the VAX, and data-race-free-0 by formalizing the above intuition in a manner that retains the advantages of each of the four models. A multiprocessor is data-race-free-1 if it guarantees sequential consistency to data-race-free programs. Data-race-free-1 unifies the four models by providing a programmer’s interface similar to the four models, and by allowing all implementations allowed by the four models. Additionally, data-race-free-1 expresses the programmer’s interface more explicitly and formally than weak ordering and the VAX, and allows an implementation not allowed by weak ordering, release consistency, or data-race-free-0, The new implementation proposal for data-race-free-1 differs from earlier implementations mainly by permitting the execution of all synchronization operations of a processor even while previous data operations of the processor are in progress. To ensure sequential consistency, two synchronizing processors exchange information to delay later operations of the second processor that conflict with an incomplete data operation of the first processor.
KW - Data-race-free-0
KW - data-race-free-1
KW - memory model
KW - release consistency
KW - sequential consistency
KW - shared-memory multiprocessor
KW - weak ordering
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U2 - 10.1109/71.242161
DO - 10.1109/71.242161
M3 - Article
AN - SCOPUS:0027608117
SN - 1045-9219
VL - 4
SP - 613
EP - 624
JO - IEEE Transactions on Parallel and Distributed Systems
JF - IEEE Transactions on Parallel and Distributed Systems
IS - 6
ER -