A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery

Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phase-locked loop (PLL) wherein a passive lead-lag analog loop filter is used to set the loop response. Large capacitors needed to achieve low jitter transfer bandwidth and a highly over-damped response to reduce jitter peaking prohibit monolithic integration of the analog loop filter [1, 2]. Digital loop filters (DLFs) that are robust to process and temperature variations have recently emerged as an alternate solution to implementing fully integrated CDRs [3-5].

Original languageEnglish (US)
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Pages440-441
Number of pages2
DOIs
StatePublished - May 12 2011
Externally publishedYes
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: Feb 20 2011Feb 24 2011

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period2/20/112/24/11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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