@inproceedings{f100fc8fdc06472abf6ffa77cbabee8c,
title = "A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery",
abstract = "A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phase-locked loop (PLL) wherein a passive lead-lag analog loop filter is used to set the loop response. Large capacitors needed to achieve low jitter transfer bandwidth and a highly over-damped response to reduce jitter peaking prohibit monolithic integration of the analog loop filter [1, 2]. Digital loop filters (DLFs) that are robust to process and temperature variations have recently emerged as an alternate solution to implementing fully integrated CDRs [3-5].",
author = "Wenjing Yin and Rajesh Inti and Amr Elshazly and Hanumolu, {Pavan Kumar}",
year = "2011",
doi = "10.1109/ISSCC.2011.5746388",
language = "English (US)",
isbn = "9781612843001",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "440--441",
booktitle = "2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011",
address = "United States",
note = "2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 ; Conference date: 20-02-2011 Through 24-02-2011",
}