A TDC-less 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery

Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu

Research output: Contribution to journalArticlepeer-review


A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The prototype digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER < 10 -12) for PRBS data sequences ranging from 27-1 to 2 31-1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.

Original languageEnglish (US)
Article number6062657
Pages (from-to)3163-3173
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Issue number12
StatePublished - Dec 2011
Externally publishedYes


  • Digital clock and data recovery circuit
  • hybrid analog/digital phase detection
  • jitter transfer bandwidth
  • linear loop dynamics

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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