TY - JOUR
T1 - A TDC-less 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery
AU - Yin, Wenjing
AU - Inti, Rajesh
AU - Elshazly, Amr
AU - Talegaonkar, Mrunmay
AU - Young, Brian
AU - Hanumolu, Pavan Kumar
N1 - Funding Information:
Manuscript received April 13, 2011; revised July 01, 2011; accepted August 01, 2011. Date of publication October 28, 2011; date of current version November 23, 2011. This paper was approved by Guest Editor Miki Moyal. This work was supported in part by Semiconductor Research Corporation (SRC) under Contract 2007-HJ-1597.
PY - 2011/12
Y1 - 2011/12
N2 - A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The prototype digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER < 10 -12) for PRBS data sequences ranging from 27-1 to 2 31-1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.
AB - A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The prototype digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER < 10 -12) for PRBS data sequences ranging from 27-1 to 2 31-1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.
KW - Digital clock and data recovery circuit
KW - hybrid analog/digital phase detection
KW - jitter transfer bandwidth
KW - linear loop dynamics
UR - http://www.scopus.com/inward/record.url?scp=82155162329&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=82155162329&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2011.2168873
DO - 10.1109/JSSC.2011.2168873
M3 - Article
AN - SCOPUS:82155162329
SN - 0018-9200
VL - 46
SP - 3163
EP - 3173
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 12
M1 - 6062657
ER -