A task-centric memory model for scalable accelerator architectures

John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Sanjay J. Patel, Matthew I. Frank

Research output: Contribution to journalArticlepeer-review


This article presents a memory model for parallel compute accelerators with task-based programming models that uses a software protocol, working in collaboration with hardware caches, to maintain a coherent, single address space view of memory without requiring hardware cache coherence. The memory model supports visual computing applications, which are becoming an important class of workloads capable of exploiting 1,000-core processors.

Original languageEnglish (US)
Article number5430737
Pages (from-to)29-39
Number of pages11
JournalIEEE Micro
Issue number1
StatePublished - Jan 2010


  • Accelerator
  • Memory model
  • Parallel architecture
  • Software coherence

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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