@article{a96dd4d578804de8b3ddc71c253c0cf4,
title = "A task-centric memory model for scalable accelerator architectures",
abstract = "This article presents a memory model for parallel compute accelerators with task-based programming models that uses a software protocol, working in collaboration with hardware caches, to maintain a coherent, single address space view of memory without requiring hardware cache coherence. The memory model supports visual computing applications, which are becoming an important class of workloads capable of exploiting 1,000-core processors.",
keywords = "Accelerator, Memory model, Parallel architecture, Software coherence",
author = "Kelm, {John H.} and Johnson, {Daniel R.} and Lumetta, {Steven S.} and Patel, {Sanjay J.} and Frank, {Matthew I.}",
note = "Funding Information: We acknowledge the support of the Focus Center for Circuit & Systems Solutions (C2S2) and the Gigascale Systems Research Center (GSRC), two of the five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation Program. We thank the Trusted ILLIAC Center at the Information Trust Institute for their generous contribution of use of their computing cluster to help us complete our research. We also thank Naveen Neelakantam, Matt R. Johnson, Aqeel Mahesri, and the anonymous reviewers for their input and feedback. John Kelm was partially supported by a fellowship from Advanced Micro Devices.",
year = "2010",
month = jan,
doi = "10.1109/MM.2010.6",
language = "English (US)",
volume = "30",
pages = "29--39",
journal = "IEEE Micro",
issn = "0272-1732",
publisher = "IEEE Computer Society",
number = "1",
}