A Systematic Design Methodology for Series-Stacked Energy Decoupling Buffers Based on Loss-Volume Pareto Optimization

The series-stacked buffer (SSB) is an active twice-line frequency energy decoupling buffer architecture in single-phase converters. The high power density and efficiency characteristics of this architecture have been recently demonstrated. However, in previous hardware work on the SSB, the energy utilization ratios of the buffer capacitors are not optimized, and the tradeoff among loss, volume, and bus voltage ripple has not been quantitatively studied. In this article, we propose a methodology that quantifies and formalizes the SSB design process into a multiobjective optimization problem, from which the loss-volume Pareto front can be solved, and an optimal control strategy for minimum loss can be determined. Design constraints, modeling of objective functions, and optimization algorithms are discussed. With realistic hardware parameters and constraints, this methodology is applied to the SSB design for a 1.5-kW, 400-V dc-bus single-phase system. The corresponding Pareto front results are studied with hardware prototypes. Compared with previous SSB hardware demonstrations, both power density and efficiency of the designed hardwares are substantially enhanced with the proposed method.