A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter

Pavan Kumar Hanumolu, Volodymyr Kratyuk, Gu Yeon Wei, Un Ku Moon

Research output: Contribution to journalArticle


A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 μm CMOS process, operates from 0.5-1.5 GHz and achieves a differential nonlinearity of less than ±0.1 ps and an integral nonlinearity of ±12 ps. The total power consumption while operating at 1 GHz is 15 mW.

Original languageEnglish (US)
Pages (from-to)414-423
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Issue number2
StatePublished - Feb 1 2008


  • Delay-locked loop (DLL)
  • Delta-sigma modulation
  • Digital-to-phase converter
  • Glitch-free phase switching
  • Noise shaping
  • Phase filter
  • Phase interpolation
  • Phase-locked loop (PLL)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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