TY - JOUR
T1 - A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter
AU - Hanumolu, Pavan Kumar
AU - Kratyuk, Volodymyr
AU - Wei, Gu Yeon
AU - Moon, Un Ku
N1 - Funding Information:
Manuscript received January 2, 2007; revised October 15, 2007. This work was supported by Intel Corporation. The test chip was fabricated by Samsung Electronics Ltd. P. K. Hanumolu and U. Moon are with the School of Electrial Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA (e-mail: [email protected]). V. Kratyuk is with Silicon Laboratories, Inc., Beaverton, OR 97006 USA. G.-Y. Wei is with SEAS, Harvard University, Cambridge, MA 02138 USA. Digital Object Identifier 10.1109/JSSC.2007.914287
PY - 2008/2
Y1 - 2008/2
N2 - A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 μm CMOS process, operates from 0.5-1.5 GHz and achieves a differential nonlinearity of less than ±0.1 ps and an integral nonlinearity of ±12 ps. The total power consumption while operating at 1 GHz is 15 mW.
AB - A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 μm CMOS process, operates from 0.5-1.5 GHz and achieves a differential nonlinearity of less than ±0.1 ps and an integral nonlinearity of ±12 ps. The total power consumption while operating at 1 GHz is 15 mW.
KW - Delay-locked loop (DLL)
KW - Delta-sigma modulation
KW - Digital-to-phase converter
KW - Glitch-free phase switching
KW - Noise shaping
KW - Phase filter
KW - Phase interpolation
KW - Phase-locked loop (PLL)
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U2 - 10.1109/JSSC.2007.914287
DO - 10.1109/JSSC.2007.914287
M3 - Article
AN - SCOPUS:38849197525
SN - 0018-9200
VL - 43
SP - 414
EP - 423
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 2
ER -