TY - GEN
T1 - A Study on Soft-Core Processor Configurations for Embedded Cryptography Applications
AU - Kueffler, Benjamin
AU - Hwu, Wen Mei
AU - El-Hadedy, Mohamed
N1 - Funding Information:
Acknowledgment. This work is supported by the IBM-ILLINOIS Center for Cognitive Computing Systems Research (C3SR) - a member of the IBM Cognitive Horizon Network, and the Applications Driving Architectures (ADA) Research Center - one of the JUMP Centers co-sponsored by SRC and DARPA, and Northrop Grumman.
Publisher Copyright:
© 2021, Springer Nature Switzerland AG.
PY - 2021
Y1 - 2021
N2 - FPGAs provide a platform for embedded designs to achieve impressive performance with minimal resources by targeting specific applications. This platform is especially desirable for embedded cryptography applications, which are increasingly needed in resource constrained embedded devices. In this work, tests were performed on the Xilinx MicroBlaze soft-core processor in order to accelerate the Rivest-Shamir-Adleman (RSA) algorithm and determine the platform’s success under metrics such as power, performance, and logic utilization. Each of these tests enabled hardware features on the processor commonly used in embedded applications in order to determine the ideal configuration for RSA applications. Minimum area, high performance, maximum frequency, and frequency optimized implementations were produced in order to survey tradeoffs that exist within these various configurations. The result of these tests indicate that targeted hardware has the ability to achieve multi-fold performance improvements compared to hardware not optimized around the RSA algorithm.
AB - FPGAs provide a platform for embedded designs to achieve impressive performance with minimal resources by targeting specific applications. This platform is especially desirable for embedded cryptography applications, which are increasingly needed in resource constrained embedded devices. In this work, tests were performed on the Xilinx MicroBlaze soft-core processor in order to accelerate the Rivest-Shamir-Adleman (RSA) algorithm and determine the platform’s success under metrics such as power, performance, and logic utilization. Each of these tests enabled hardware features on the processor commonly used in embedded applications in order to determine the ideal configuration for RSA applications. Minimum area, high performance, maximum frequency, and frequency optimized implementations were produced in order to survey tradeoffs that exist within these various configurations. The result of these tests indicate that targeted hardware has the ability to achieve multi-fold performance improvements compared to hardware not optimized around the RSA algorithm.
KW - Embedded cryptography
KW - FPGA
KW - MicroBlaze
KW - Soft-core processor
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U2 - 10.1007/978-3-030-63092-8_53
DO - 10.1007/978-3-030-63092-8_53
M3 - Conference contribution
AN - SCOPUS:85096476107
SN - 9783030630911
T3 - Advances in Intelligent Systems and Computing
SP - 796
EP - 809
BT - Proceedings of the Future Technologies Conference, FTC 2020, Volume 3
A2 - Arai, Kohei
A2 - Kapoor, Supriya
A2 - Bhatia, Rahul
PB - Springer Science and Business Media Deutschland GmbH
T2 - Future Technologies Conference, FTC 2020
Y2 - 5 November 2020 through 6 November 2020
ER -