A study of memory-aware scheduling in message driven parallel programs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a simple, but powerful memory-aware scheduling mechanism that adaptively schedules tasks in a message driven distributed-memory parallel program. The scheduler adapts its behavior whenever memory usage exceeds a threshold by scheduling tasks known to reduce memory usage. The usefulness of the scheduler and its low overhead are demonstrated in the context of an LU matrix factorization program. In the LU program, only a single additional line of code is required to make use of the new general-purpose memory-aware scheduling mechanism. Without memory-aware scheduling, the LU program can only run with small problem sizes, but with the new memory-aware scheduling, the program scales to larger problem sizes.

Original languageEnglish (US)
Title of host publication17th International Conference on High Performance Computing, HiPC 2010
PublisherIEEE Computer Society
ISBN (Print)9781424485185
DOIs
StatePublished - 2010
Event17th International Conference on High Performance Computing, HiPC 2010 - Goa, India
Duration: Dec 19 2010Dec 22 2010

Publication series

Name17th International Conference on High Performance Computing, HiPC 2010

Other

Other17th International Conference on High Performance Computing, HiPC 2010
Country/TerritoryIndia
CityGoa
Period12/19/1012/22/10

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Theoretical Computer Science

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