Abstract
Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the backplane community due to the desire for higher I/O throughput, ease of design portability, and flexibility. However, the power dissipation in such receivers is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion ratio (SNDR) and effective-number-of-bit (ENOB) as performance metrics as these are the standard for generic ADC design. This paper studies the use of information-based metrics such as bit-error-rate (BER) to design a BER-optimal ADC (BOA) for serial links. Channel parameters such as the m-clustering value and the threshold non-uniformity metric ht are introduced and employed to quantify the BER improvement achieved by a BOA over a conventional uniform ADC (CUA) in a receiver. Analytical expressions for BER improvement are derived and validated through simulations. A prototype BOA is designed, fabricated and tested in a 1.2 V, 90 nm LP CMOS process to verify the results of this study. BOA's variable-threshold and variable-resolution configurations are implemented via an 8-bit single-core, multiple-output passive digital-to-analog converter (DAC), which incurs an additional power overhead of < 0.1% (approximately 50 μW). Measurement results show examples in which the BER achieved by the 3-bit BOA receiver is lower by a factor of 109 and 1010, as compared to the 4-bit and 3-bit CUA receivers, respectively, at a data rate of 4-Gb/s and a transmitted signal amplitude of 180 mVppd.
| Original language | English (US) |
|---|---|
| Article number | 7486052 |
| Pages (from-to) | 693-704 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 63 |
| Issue number | 5 |
| DOIs | |
| State | Published - May 2016 |
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Keywords
- Analog-to-digital converter
- bit-error-rate
- energy efficiency
- mixed-signal
- serial links
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A Study of BER-Optimal ADC-Based Receiver for Serial Links. / Lin, Yingyan; Keel, Min Sun; Faust, Adam; Xu, Aolin; Shanbhag, Naresh R; Rosenbaum, Elyse; Singer, Andrew Carl.
In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 63, No. 5, 7486052, 05.2016, p. 693-704.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A Study of BER-Optimal ADC-Based Receiver for Serial Links
AU - Lin, Yingyan
AU - Keel, Min Sun
AU - Faust, Adam
AU - Xu, Aolin
AU - Shanbhag, Naresh R
AU - Rosenbaum, Elyse
AU - Singer, Andrew Carl
PY - 2016/5
Y1 - 2016/5
N2 - Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the backplane community due to the desire for higher I/O throughput, ease of design portability, and flexibility. However, the power dissipation in such receivers is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion ratio (SNDR) and effective-number-of-bit (ENOB) as performance metrics as these are the standard for generic ADC design. This paper studies the use of information-based metrics such as bit-error-rate (BER) to design a BER-optimal ADC (BOA) for serial links. Channel parameters such as the m-clustering value and the threshold non-uniformity metric ht are introduced and employed to quantify the BER improvement achieved by a BOA over a conventional uniform ADC (CUA) in a receiver. Analytical expressions for BER improvement are derived and validated through simulations. A prototype BOA is designed, fabricated and tested in a 1.2 V, 90 nm LP CMOS process to verify the results of this study. BOA's variable-threshold and variable-resolution configurations are implemented via an 8-bit single-core, multiple-output passive digital-to-analog converter (DAC), which incurs an additional power overhead of < 0.1% (approximately 50 μW). Measurement results show examples in which the BER achieved by the 3-bit BOA receiver is lower by a factor of 109 and 1010, as compared to the 4-bit and 3-bit CUA receivers, respectively, at a data rate of 4-Gb/s and a transmitted signal amplitude of 180 mVppd.
AB - Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the backplane community due to the desire for higher I/O throughput, ease of design portability, and flexibility. However, the power dissipation in such receivers is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion ratio (SNDR) and effective-number-of-bit (ENOB) as performance metrics as these are the standard for generic ADC design. This paper studies the use of information-based metrics such as bit-error-rate (BER) to design a BER-optimal ADC (BOA) for serial links. Channel parameters such as the m-clustering value and the threshold non-uniformity metric ht are introduced and employed to quantify the BER improvement achieved by a BOA over a conventional uniform ADC (CUA) in a receiver. Analytical expressions for BER improvement are derived and validated through simulations. A prototype BOA is designed, fabricated and tested in a 1.2 V, 90 nm LP CMOS process to verify the results of this study. BOA's variable-threshold and variable-resolution configurations are implemented via an 8-bit single-core, multiple-output passive digital-to-analog converter (DAC), which incurs an additional power overhead of < 0.1% (approximately 50 μW). Measurement results show examples in which the BER achieved by the 3-bit BOA receiver is lower by a factor of 109 and 1010, as compared to the 4-bit and 3-bit CUA receivers, respectively, at a data rate of 4-Gb/s and a transmitted signal amplitude of 180 mVppd.
KW - Analog-to-digital converter
KW - bit-error-rate
KW - energy efficiency
KW - mixed-signal
KW - serial links
UR - http://www.scopus.com/inward/record.url?scp=84973548635&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84973548635&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2016.2529284
DO - 10.1109/TCSI.2016.2529284
M3 - Article
AN - SCOPUS:84973548635
VL - 63
SP - 693
EP - 704
JO - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
JF - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
SN - 1549-8328
IS - 5
M1 - 7486052
ER -