A Soft Error Rate Analysis (SERA) methodology

Ming Zhang, Naresh R. Shanbhag

Research output: Contribution to journalConference article

Abstract

We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. SERA achieves five orders of magnitude speed-up over Monte Carlo based simulation approaches with less than 5% error. Dependence of soft error rate (SER) of combinational circuits on supply voltage, clock period, latching window, circuit topology, and input vector values are explicitly captured and studied for a typical 0.18 μm CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an "SER peaking" phenomenon in multipliers is observed where the center bits have an SER that is orders of magnitude greater than that of LSBs and MSBs.

Original languageEnglish (US)
Article number2A.3
Pages (from-to)111-118
Number of pages8
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
StatePublished - Dec 1 2004
EventICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 7 2004Nov 11 2004

Fingerprint

Combinatorial circuits
Electric network topology
Circuit simulation
Graph theory
Electric potential
Clocks
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

A Soft Error Rate Analysis (SERA) methodology. / Zhang, Ming; Shanbhag, Naresh R.

In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 01.12.2004, p. 111-118.

Research output: Contribution to journalConference article

@article{119f3ad959b3408394256032e6abcba6,
title = "A Soft Error Rate Analysis (SERA) methodology",
abstract = "We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. SERA achieves five orders of magnitude speed-up over Monte Carlo based simulation approaches with less than 5{\%} error. Dependence of soft error rate (SER) of combinational circuits on supply voltage, clock period, latching window, circuit topology, and input vector values are explicitly captured and studied for a typical 0.18 μm CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an {"}SER peaking{"} phenomenon in multipliers is observed where the center bits have an SER that is orders of magnitude greater than that of LSBs and MSBs.",
author = "Ming Zhang and Shanbhag, {Naresh R.}",
year = "2004",
month = "12",
day = "1",
language = "English (US)",
pages = "111--118",
journal = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers",
issn = "1092-3152",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - A Soft Error Rate Analysis (SERA) methodology

AU - Zhang, Ming

AU - Shanbhag, Naresh R.

PY - 2004/12/1

Y1 - 2004/12/1

N2 - We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. SERA achieves five orders of magnitude speed-up over Monte Carlo based simulation approaches with less than 5% error. Dependence of soft error rate (SER) of combinational circuits on supply voltage, clock period, latching window, circuit topology, and input vector values are explicitly captured and studied for a typical 0.18 μm CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an "SER peaking" phenomenon in multipliers is observed where the center bits have an SER that is orders of magnitude greater than that of LSBs and MSBs.

AB - We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. SERA achieves five orders of magnitude speed-up over Monte Carlo based simulation approaches with less than 5% error. Dependence of soft error rate (SER) of combinational circuits on supply voltage, clock period, latching window, circuit topology, and input vector values are explicitly captured and studied for a typical 0.18 μm CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an "SER peaking" phenomenon in multipliers is observed where the center bits have an SER that is orders of magnitude greater than that of LSBs and MSBs.

UR - http://www.scopus.com/inward/record.url?scp=16244391105&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=16244391105&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:16244391105

SP - 111

EP - 118

JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

SN - 1092-3152

M1 - 2A.3

ER -