A single-chip pipelined 2-D FIR filter using residue arithmetic

Naresh R. Shanbhag, Raymond E. Siferd

Research output: Contribution to conferencePaper

Abstract

The authors present novel circuits for residue arithmetic, which have been configured to form a 3 × 3 finite impulse response (FIR) filter with programmable coefficients. The filter has a pipelined architecture and includes testability in the form of scan path. Area efficient circuits for residue adders, subtractors, and binary-to-residue converters have been designed. An encoding scheme has been used to reduce the residue multiplier area. A tree architecture for residue-to-binary conversion has been developed. The filter is timed with a two-phase clock, which has an estimated frequency of 15 Mhz.

Original languageEnglish (US)
Pages98-101
Number of pages4
StatePublished - Dec 1 1990
Externally publishedYes
EventProceedings of the IEEE 1990 National Aerospace and Electronics Conference - NAECON 1990 - Dayton, OH, USA
Duration: May 21 1990May 25 1990

Other

OtherProceedings of the IEEE 1990 National Aerospace and Electronics Conference - NAECON 1990
CityDayton, OH, USA
Period5/21/905/25/90

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shanbhag, N. R., & Siferd, R. E. (1990). A single-chip pipelined 2-D FIR filter using residue arithmetic. 98-101. Paper presented at Proceedings of the IEEE 1990 National Aerospace and Electronics Conference - NAECON 1990, Dayton, OH, USA, .