A Single-Chip Pipelined 2-D FIR Filter Using Residue Arithmetic

Naresh R. Shanbhag, Raymond E. Siferd

Research output: Contribution to journalArticle

Abstract

Presented in this paper are novel circuits and architecture for residue arithmetic. These circuits are aimed towards fast and area-efficient single-chip implementation of digital signal processors. This has been achieved by following an algorithmic approach as opposed to the conventional look-up table approach. As a result, substantial area savings have resulted. The circuits include the residue adder, residue multiplier, binary-to-residue converter, and residue-to-binary converter. Based on these circuits, a prototype single-chip, 3×3, finite impulse response (FIR), variable coefficient, linear-phase filter has been designed and fabricated in standard 2-μm CMOS technology. The filter has a pipelined architecture to increase the throughput. Testability in the form of scan-path registers has been incorporated. An interesting feature of this unique combination of residue arithmetic and scan-path testing is the possible trade-off available between the precision of the filter coefficients and the image data. The chip has a die size of 6.6 X 4.2 mm2, dissipates 220 mW of power, and is synchronized with a 180-ns clock cycle.

Original languageEnglish (US)
Pages (from-to)796-805
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume26
Issue number5
DOIs
StatePublished - May 1991
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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