A Single-Chip Pipelined 2-D FIR Filter Using Residue Arithmetic

Naresh R. Shanbhag, Raymond E. Siferd

Research output: Contribution to journalArticle

Abstract

Presented in this paper are novel circuits and architecture for residue arithmetic. These circuits are aimed towards fast and area-efficient single-chip implementation of digital signal processors. This has been achieved by following an algorithmic approach as opposed to the conventional look-up table approach. As a result, substantial area savings have resulted. The circuits include the residue adder, residue multiplier, binary-to-residue converter, and residue-to-binary converter. Based on these circuits, a prototype single-chip, 3×3, finite impulse response (FIR), variable coefficient, linear-phase filter has been designed and fabricated in standard 2-μm CMOS technology. The filter has a pipelined architecture to increase the throughput. Testability in the form of scan-path registers has been incorporated. An interesting feature of this unique combination of residue arithmetic and scan-path testing is the possible trade-off available between the precision of the filter coefficients and the image data. The chip has a die size of 6.6 X 4.2 mm2, dissipates 220 mW of power, and is synchronized with a 180-ns clock cycle.

Original languageEnglish (US)
Pages (from-to)796-805
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume26
Issue number5
DOIs
StatePublished - May 1991

Fingerprint

FIR filters
Networks (circuits)
Adders
Digital signal processors
Impulse response
Clocks
Throughput
Testing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A Single-Chip Pipelined 2-D FIR Filter Using Residue Arithmetic. / Shanbhag, Naresh R.; Siferd, Raymond E.

In: IEEE Journal of Solid-State Circuits, Vol. 26, No. 5, 05.1991, p. 796-805.

Research output: Contribution to journalArticle

@article{9a7c1d480ca849dc96bd72de5039d2f3,
title = "A Single-Chip Pipelined 2-D FIR Filter Using Residue Arithmetic",
abstract = "Presented in this paper are novel circuits and architecture for residue arithmetic. These circuits are aimed towards fast and area-efficient single-chip implementation of digital signal processors. This has been achieved by following an algorithmic approach as opposed to the conventional look-up table approach. As a result, substantial area savings have resulted. The circuits include the residue adder, residue multiplier, binary-to-residue converter, and residue-to-binary converter. Based on these circuits, a prototype single-chip, 3×3, finite impulse response (FIR), variable coefficient, linear-phase filter has been designed and fabricated in standard 2-μm CMOS technology. The filter has a pipelined architecture to increase the throughput. Testability in the form of scan-path registers has been incorporated. An interesting feature of this unique combination of residue arithmetic and scan-path testing is the possible trade-off available between the precision of the filter coefficients and the image data. The chip has a die size of 6.6 X 4.2 mm2, dissipates 220 mW of power, and is synchronized with a 180-ns clock cycle.",
author = "Shanbhag, {Naresh R.} and Siferd, {Raymond E.}",
year = "1991",
month = "5",
doi = "10.1109/4.78251",
language = "English (US)",
volume = "26",
pages = "796--805",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - A Single-Chip Pipelined 2-D FIR Filter Using Residue Arithmetic

AU - Shanbhag, Naresh R.

AU - Siferd, Raymond E.

PY - 1991/5

Y1 - 1991/5

N2 - Presented in this paper are novel circuits and architecture for residue arithmetic. These circuits are aimed towards fast and area-efficient single-chip implementation of digital signal processors. This has been achieved by following an algorithmic approach as opposed to the conventional look-up table approach. As a result, substantial area savings have resulted. The circuits include the residue adder, residue multiplier, binary-to-residue converter, and residue-to-binary converter. Based on these circuits, a prototype single-chip, 3×3, finite impulse response (FIR), variable coefficient, linear-phase filter has been designed and fabricated in standard 2-μm CMOS technology. The filter has a pipelined architecture to increase the throughput. Testability in the form of scan-path registers has been incorporated. An interesting feature of this unique combination of residue arithmetic and scan-path testing is the possible trade-off available between the precision of the filter coefficients and the image data. The chip has a die size of 6.6 X 4.2 mm2, dissipates 220 mW of power, and is synchronized with a 180-ns clock cycle.

AB - Presented in this paper are novel circuits and architecture for residue arithmetic. These circuits are aimed towards fast and area-efficient single-chip implementation of digital signal processors. This has been achieved by following an algorithmic approach as opposed to the conventional look-up table approach. As a result, substantial area savings have resulted. The circuits include the residue adder, residue multiplier, binary-to-residue converter, and residue-to-binary converter. Based on these circuits, a prototype single-chip, 3×3, finite impulse response (FIR), variable coefficient, linear-phase filter has been designed and fabricated in standard 2-μm CMOS technology. The filter has a pipelined architecture to increase the throughput. Testability in the form of scan-path registers has been incorporated. An interesting feature of this unique combination of residue arithmetic and scan-path testing is the possible trade-off available between the precision of the filter coefficients and the image data. The chip has a die size of 6.6 X 4.2 mm2, dissipates 220 mW of power, and is synchronized with a 180-ns clock cycle.

UR - http://www.scopus.com/inward/record.url?scp=0026157891&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026157891&partnerID=8YFLogxK

U2 - 10.1109/4.78251

DO - 10.1109/4.78251

M3 - Article

AN - SCOPUS:0026157891

VL - 26

SP - 796

EP - 805

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -