A semi-synchronous SAR ADC

Tao Tong, Pavan K. Hanumolu, Gabor C. Temes

Research output: Contribution to journalArticlepeer-review


A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analogto- digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.

Original languageEnglish (US)
Pages (from-to)407-410
Number of pages4
JournalAnalog Integrated Circuits and Signal Processing
Issue number3
StatePublished - Jun 2012
Externally publishedYes


  • Analog-to-digital converters
  • Dynamic clocking scheme
  • Successiveapproximation conversion

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

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