A semi-synchronous SAR ADC

Tao Tong; Pavan K. Hanumolu; Gabor C. Temes

doi:10.1007/s10470-011-9769-4

A semi-synchronous SAR ADC

Tao Tong, Pavan K. Hanumolu, Gabor C. Temes

Research output: Contribution to journal › Article › peer-review

Abstract

A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analogto- digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.

Original language	English (US)
Pages (from-to)	407-410
Number of pages	4
Journal	Analog Integrated Circuits and Signal Processing
Volume	71
Issue number	3
DOIs	https://doi.org/10.1007/s10470-011-9769-4
State	Published - Jun 2012
Externally published	Yes

Keywords

Analog-to-digital converters
Dynamic clocking scheme
Successiveapproximation conversion

ASJC Scopus subject areas

Signal Processing
Hardware and Architecture
Surfaces, Coatings and Films

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10.1007/s10470-011-9769-4

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A semi-synchronous SAR ADC

Abstract

Keywords

ASJC Scopus subject areas

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