On-chip RC-based frequency references are increasingly being used to generate device clocks. They consume lower power, occupy a small area, and do not require costly off-chip components. However, poor frequency accuracy resulting from their non-linear temperature sensitivity has limited their usage to systems that can tolerate large frequency inaccuracy (1%). Several efforts are underway to reduce the inaccuracy and extend their use to real-time clock sources that mandate a more stringent inaccuracy (±250ppm). Among the reported schemes, those based on 2-point digital trim methods described in  and  are most effective in achieving excellent power efficiency (1μW/MHz in  at ±530ppm inaccuracy) or small frequency inaccuracy (±400ppm in  at 25μW/MHz). However, uncompensated higher-order temperature coefficient (TC) prevents reducing their inaccuracy further. Also,  requires resistors with opposing TCs, which may not be available in all processes. Higher-order compensation schemes based on finely-tuned analog networks  or correction polynomials  can alleviate some of these drawbacks, but they are susceptible to circuit-level imperfections  or exhibit poor power efficiency (100μW/MHz) . This paper presents techniques to reduce the TC nonlinearity and proposes methods for performing first-and second-order compensation. The 100MHz RC oscillator prototype achieves an inaccuracy of ±140ppm (2.1ppm/°C) with a power efficiency of 1μW/MHz.