A scalable approach for throughput estimation of timing speculation designs

Viraj Athavale, Jayanand Asok Kumar, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Timing speculation is a 'better-than-worst-case' design methodology that tunes a digital circuit to its common-case delay. The average throughput of a speculation-based circuit can be estimated using the probability with which input patterns result in timing errors. In this paper, we present a scalable approach to compute the exact probabilities of the occurrence of timing errors at the gate level. We use Timed Characteristic Functions (TCFs) to compute the exact values of the probabilities. In order to improve the scalability, we decompose large circuits into smaller sub-circuits and restrict the TCF computation to these sub-circuits. Instead of substituting the expression for TCF of one sub-circuit into another, we propagate only the computed error probabilities. We demonstrate our technique on gate level combinational circuits from MCNC benchmarks.

Original languageEnglish (US)
Title of host publication2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010
Pages1234-1237
Number of pages4
DOIs
StatePublished - Sep 20 2010
Event53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010 - Seattle, WA, United States
Duration: Aug 1 2010Aug 4 2010

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010
CountryUnited States
CitySeattle, WA
Period8/1/108/4/10

Fingerprint

Throughput
Networks (circuits)
Combinatorial circuits
Digital circuits
Scalability

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Athavale, V., Kumar, J. A., & Vasudevan, S. (2010). A scalable approach for throughput estimation of timing speculation designs. In 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010 (pp. 1234-1237). [5548771] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2010.5548771

A scalable approach for throughput estimation of timing speculation designs. / Athavale, Viraj; Kumar, Jayanand Asok; Vasudevan, Shobha.

2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010. 2010. p. 1234-1237 5548771 (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Athavale, V, Kumar, JA & Vasudevan, S 2010, A scalable approach for throughput estimation of timing speculation designs. in 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010., 5548771, Midwest Symposium on Circuits and Systems, pp. 1234-1237, 53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010, Seattle, WA, United States, 8/1/10. https://doi.org/10.1109/MWSCAS.2010.5548771
Athavale V, Kumar JA, Vasudevan S. A scalable approach for throughput estimation of timing speculation designs. In 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010. 2010. p. 1234-1237. 5548771. (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2010.5548771
Athavale, Viraj ; Kumar, Jayanand Asok ; Vasudevan, Shobha. / A scalable approach for throughput estimation of timing speculation designs. 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010. 2010. pp. 1234-1237 (Midwest Symposium on Circuits and Systems).
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