A routing approach to reduce glitches in low power FPGAs

Research output: Contribution to journalArticle

Abstract

This paper presents a novel approach to reduce dynamic power in field-programmable gate arrays (FPGAs) by reducing glitches during routing. It finds alternative routes for early-arriving signals so that signal arrival times at look-up tables are aligned. We developed an efficient algorithm to find routes with target delays and then built a glitch-aware router aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 27% reduction in glitch power is achieved, which translates into an 11% reduction in dynamic power, compared to the glitch-unaware versatile place and route's router.

Original languageEnglish (US)
Article number5395747
Pages (from-to)235-240
Number of pages6
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume29
Issue number2
DOIs
StatePublished - Feb 1 2010

Fingerprint

Field programmable gate arrays (FPGA)
Routers
Routing algorithms
Experiments

Keywords

  • FPGA
  • Glitch reduction
  • Low power
  • Path balancing
  • Routing

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

A routing approach to reduce glitches in low power FPGAs. / Dinh, Quang; Chen, Deming; Wong, Martin D F.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, 5395747, 01.02.2010, p. 235-240.

Research output: Contribution to journalArticle

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