A routing approach to reduce glitches in low power FPGAs

Quang Dinh; Deming Chen; Martin D.F. Wong

doi:10.1109/TCAD.2009.2035564

A routing approach to reduce glitches in low power FPGAs

Quang Dinh, Deming Chen, Martin D.F. Wong

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents a novel approach to reduce dynamic power in field-programmable gate arrays (FPGAs) by reducing glitches during routing. It finds alternative routes for early-arriving signals so that signal arrival times at look-up tables are aligned. We developed an efficient algorithm to find routes with target delays and then built a glitch-aware router aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 27% reduction in glitch power is achieved, which translates into an 11% reduction in dynamic power, compared to the glitch-unaware versatile place and route's router.

Original language	English (US)
Article number	5395747
Pages (from-to)	235-240
Number of pages	6
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	29
Issue number	2
DOIs	https://doi.org/10.1109/TCAD.2009.2035564
State	Published - Feb 2010

Keywords

FPGA
Glitch reduction
Low power
Path balancing
Routing

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Online availability

10.1109/TCAD.2009.2035564

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title = "A routing approach to reduce glitches in low power FPGAs",

abstract = "This paper presents a novel approach to reduce dynamic power in field-programmable gate arrays (FPGAs) by reducing glitches during routing. It finds alternative routes for early-arriving signals so that signal arrival times at look-up tables are aligned. We developed an efficient algorithm to find routes with target delays and then built a glitch-aware router aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 27% reduction in glitch power is achieved, which translates into an 11% reduction in dynamic power, compared to the glitch-unaware versatile place and route's router.",

keywords = "FPGA, Glitch reduction, Low power, Path balancing, Routing",

author = "Quang Dinh and Deming Chen and Wong, {Martin D.F.}",

note = "Funding Information: Manuscript received June 13, 2009; revised August 19, 2009. Current version published January 22, 2010. This work was supported in part by Altera Corporation, San Jose, CA, by National Science Foundation (NSF) Grant CCF-0746608, and by NSF Grant CCF-0701821. This work is a transaction version of the authors{\textquoteright} work in the Proceedings of International Symposium on Physical Design, 2009 [6]. This paper was recommended by Associate Editor P. Saxena.",

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AU - Chen, Deming

AU - Wong, Martin D.F.

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AB - This paper presents a novel approach to reduce dynamic power in field-programmable gate arrays (FPGAs) by reducing glitches during routing. It finds alternative routes for early-arriving signals so that signal arrival times at look-up tables are aligned. We developed an efficient algorithm to find routes with target delays and then built a glitch-aware router aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 27% reduction in glitch power is achieved, which translates into an 11% reduction in dynamic power, compared to the glitch-unaware versatile place and route's router.

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KW - Low power

KW - Path balancing

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A routing approach to reduce glitches in low power FPGAs

Abstract

Keywords

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