A routing approach to reduce glitches in low power FPGAS

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routing step. This approach involves finding alternative routes for early-arriving signals, so that signal arrival times at LUTs are aligned and no glitches are generated. This approach does not require additional circuitry to balance signals as done in previous work, but uses the available programmable routing resources instead. We develop an efficient algorithm to find routes with target delays. Based on this algorithm, we then build a glitch-aware router, named GlitchReroute, aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 23% reduction in glitch power is achieved, which translates into a 9.8% reduction in dynamic power, compared to the glitch-unaware VPR router.

Original languageEnglish (US)
Title of host publicationProceedings of the 2009 International Symposium on Physical Design, ISPD'09
Number of pages7
StatePublished - 2009
Event2009 International Symposium on Physical Design, ISPD'09 - San Diego, CA, United States
Duration: Mar 29 2009Apr 1 2009

Publication series

NameProceedings of the International Symposium on Physical Design


Other2009 International Symposium on Physical Design, ISPD'09
Country/TerritoryUnited States
CitySan Diego, CA


  • FPGAs
  • Glitch reduction
  • Low power
  • Path balancing
  • Routing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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