A risc central processing unit for a massivelly parallel architecture

F. Cappello, J. L. Bechennec, D. Etiemble

Research output: Contribution to journalArticlepeer-review

Abstract

We present the CPU of a message-passing Massively Parallel Architecture. It has an efficient reduced instruction set to execute a simple lexical LISP language. With a 1.5 μm CMOS technology, the chip area is approximatively 10 mm2, to be compatible with a 1 cm2 single chip including local memory and a hardwared Communication Unit.

Original languageEnglish (US)
Pages (from-to)33-39
Number of pages7
JournalMicroprocessing and Microprogramming
Volume30
Issue number1-5
DOIs
StatePublished - Aug 1990
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

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