A risc central processing unit for a massivelly parallel architecture

F. Cappello; J. L. Bechennec; D. Etiemble

doi:10.1016/0165-6074(90)90214-T

A risc central processing unit for a massivelly parallel architecture

F. Cappello, J. L. Bechennec, D. Etiemble

Research output: Contribution to journal › Article › peer-review

Abstract

We present the CPU of a message-passing Massively Parallel Architecture. It has an efficient reduced instruction set to execute a simple lexical LISP language. With a 1.5 μm CMOS technology, the chip area is approximatively 10 mm², to be compatible with a 1 cm² single chip including local memory and a hardwared Communication Unit.

Original language	English (US)
Pages (from-to)	33-39
Number of pages	7
Journal	Microprocessing and Microprogramming
Volume	30
Issue number	1-5
DOIs	https://doi.org/10.1016/0165-6074(90)90214-T
State	Published - Aug 1990
Externally published	Yes

ASJC Scopus subject areas

Engineering(all)

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10.1016/0165-6074(90)90214-T

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title = "A risc central processing unit for a massivelly parallel architecture",

abstract = "We present the CPU of a message-passing Massively Parallel Architecture. It has an efficient reduced instruction set to execute a simple lexical LISP language. With a 1.5 μm CMOS technology, the chip area is approximatively 10 mm2, to be compatible with a 1 cm2 single chip including local memory and a hardwared Communication Unit.",

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year = "1990",

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A risc central processing unit for a massivelly parallel architecture

Abstract

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