A reference-less clock and data recovery circuit using phase-rotating phase-locked loop

Guanghua Shu, Saurabh Saxena, Woo Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu

Research output: Contribution to journalArticlepeer-review

Abstract

A reference-less half-rate digital clock and data recovery (CDR) circuit employing a phase-rotating phase-locked loop (PRPLL) as phase interpolator is presented. By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain. Fabricated in a 90 nm CMOS process, the prototype CDR achieves error-free operation (BER < 10-12) with PRBS data sequences ranging from PRBS7 to PRBS31. At 5 Gb/s, it consumes 13.1 mW power and achieves a recovered clock long-term jitter of 5.0 ps rms44.0 pspp when operating with PRBS31 input data. The measured JTRAN bandwidth is 2 MHz and JTOL corner frequency is 16 MHz. The CDR is tolerant to 110 mVpp of sinusoidal noise on the DCO supply voltage at the worst case noise frequency of 7 MHz. At 2.5 GHz, the PRPLL consumes 2.9 mW and achieves 134 dBc/Hz phase noise at 1 MHz frequency offset. The differential and integral non-linearity of its digital-to-phase transfer characteristic are within ±0.2 LSB and ±0.4 LSB, respectively.

Original languageEnglish (US)
Article number6712167
Pages (from-to)1036-1047
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume49
Issue number4
DOIs
StatePublished - Apr 2014

Keywords

  • DCO
  • High speed serial link
  • clock and data recovery
  • decouple JTRAN/JTOL
  • digital CDR
  • digital phase-locked loop
  • jitter peaking
  • phase interpolator
  • phase-rotating PLL
  • reference-less FLL
  • supply regulator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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