A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults

Keyphrases

• Reconfigurable 100%
• Latency 100%
• Network on chip 100%
• Permanent Fault 100%
• Chip Performance 100%
• Fault-tolerant Routing Algorithm 100%
• Intermittent Fault 100%
• Negative Effects 50%
• On chip 50%
• System Operation 50%
• Fault Tolerance 50%
• Semiconductor Industry 50%
• Lower Average 50%
• High Reliability 50%
• Deep Submicron Technology 50%
• Power Consumption 50%
• Faulty Components 50%
• Message Latency 50%
• Chip Component 50%
• Fault-tolerant Strategy 50%

Computer Science

• Networks on Chips 100%
• Permanent Fault 100%
• fault tolerant routing 100%
• Tolerant Routing Algorithm 100%
• Experimental Result 50%
• High Reliability 50%
• Power Consumption 50%
• Fault Tolerant 50%
• fault-tolerance 50%
• System Operation 50%
• Negative Effect 50%
• Faulty Component 50%
• Message Latency 50%