A real system evaluation of hardware atomicity for software speculation

Naveen Neelakantam, David R. Ditzel, Craig Zilles

Research output: Contribution to journalArticlepeer-review


In this paper we evaluate the atomic region compiler abstraction by incorporating it into a commercial system. We find that atomic regions are simple and intuitive to integrate into an x86 binary-translation system. Furthermore, doing so trivially enables additional optimization opportunities beyond that achievable by a high-performance dynamic optimizer, which already implements superblocks. We show that atomic regions can suffer from severe performance penalties if misspeculations are left uncontrolled, but that a simple software control mechanism is sufficient to reign in all detrimental side-effects. We evaluate using full reference runs of the SPEC CPU2000 integer benchmarks and find that atomic regions enable up to a 9% (3% on average) improvement beyond the performance of a tuned product. These performance improvements are achieved without any negative side effects. Performance side effects such as code bloat are absent with atomic regions; in fact, static code size is reduced. The hardware necessary is synergistic with other needs and was already available on the commercial product used in our evaluation. Finally, the software complexity is minimal as a single developer was able to incorporate atomic regions into a sophisticated 300,000 line code base in three months, despite never having seen the translator source code beforehand.

Original languageEnglish (US)
Pages (from-to)29-38
Number of pages10
JournalACM SIGPLAN Notices
Issue number3
StatePublished - Mar 2010


  • Atomicity
  • Checkpoint
  • Dynamic translation
  • Optimization
  • Speculation

ASJC Scopus subject areas

  • General Computer Science


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