TY - GEN
T1 - A provably good algorithm for high performance bus routing
AU - Ozdal, Muhammet Mustafa
AU - Wong, Martin D.F.
PY - 2004
Y1 - 2004
N2 - As the clock frequencies used in industrial applications increase, the timing requirements on routing problems become tighter, and current routing tools can not successfully handle these constraints anymore. In this paper, we focus on the high-performance single-layer bus routing problem, where the objective is to match the lengths of all nets belonging to each bus. An effective approach to solve this problem is to allocate extra routing resources around short nets during routing; and use those resources for length extension afterwards. We first propose a provably optimal algorithm for routing nets with min-area max-length constraints. Then, we extend this algorithm to the case where minimum constraints are given as exact length bounds. We also prove that this algorithm is optimal within a constant factor. Both algorithms proposed are also shown to be scalable for large circuits, since the respective time complexities are O(A) and O(AlogA), where A is the area of the intermediate region between chips.
AB - As the clock frequencies used in industrial applications increase, the timing requirements on routing problems become tighter, and current routing tools can not successfully handle these constraints anymore. In this paper, we focus on the high-performance single-layer bus routing problem, where the objective is to match the lengths of all nets belonging to each bus. An effective approach to solve this problem is to allocate extra routing resources around short nets during routing; and use those resources for length extension afterwards. We first propose a provably optimal algorithm for routing nets with min-area max-length constraints. Then, we extend this algorithm to the case where minimum constraints are given as exact length bounds. We also prove that this algorithm is optimal within a constant factor. Both algorithms proposed are also shown to be scalable for large circuits, since the respective time complexities are O(A) and O(AlogA), where A is the area of the intermediate region between chips.
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U2 - 10.1109/ICCAD.2004.1382690
DO - 10.1109/ICCAD.2004.1382690
M3 - Conference contribution
AN - SCOPUS:16244418382
SN - 0780387023
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 830
EP - 837
BT - ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
T2 - ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Y2 - 7 November 2004 through 11 November 2004
ER -