TY - JOUR
T1 - A Polynomial Time-Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem
AU - Huang, Li Da
AU - Tang, Xiaoping
AU - Xiang, Hua
AU - Wong, D. F.
AU - Liu, I. Min
N1 - Funding Information:
Manuscript received May 15, 2002; revised April 22, 2003. This work was partially supported by the National Science Foundation under grant CCR-9912390. This paper was recommended by Associate Editor C.-K. Cheng. L.-D. Huang is with the Department of Computer Sciences, University of Texas, Austin, TX 78712 USA (e-mail: [email protected]). X. Tang and I.-M. Liu are with Cadence Inc., San Jose, CA 95134 USA. H. Xiang is with the Computer Sciences Department, University of Illinois, Urbana–Champaign, Urbana, IL 61801 USA. D. F. Wong is with the Electrical and Computer Engineering Department, University of Illinois, Urbana-Champaign, IL 61801 USA. Digital Object Identifier 10.1109/TCAD.2003.819888
PY - 2004/1
Y1 - 2004/1
N2 - Antenna problem is a phenomenon of plasma-induced gate-oxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especially in deep submicron technology using high-density plasma. Diode insertion is a very effective way to solve this problem. Ideally, diodes are inserted directly under the wires that violate antenna rules. But in today's high-density VLSI layouts, there is simply not enough room for "under-the-wire" diode insertion for all wires. Thus, it is necessary to insert many diodes at legal "off-wire" locations and extend the antenna-rule violating wires to connect to their respective diodes. Previously, only simple heuristic algorithms were available for this diode insertion and routing problem. In this paper, we show that the diode insertion and routing problem for an arbitrary given number of routing layers can be optimally solved in polynomial time. Our algorithm guarantees finding a feasible diode insertion and routing solution whenever one exists. Moreover, we can guarantee to find a feasible solution to minimize a cost function of the form α · L + β · N, where L is the total length of extension wires and N is the total number of vias on the extension wires. Experimental results show that our algorithm is very efficient.
AB - Antenna problem is a phenomenon of plasma-induced gate-oxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especially in deep submicron technology using high-density plasma. Diode insertion is a very effective way to solve this problem. Ideally, diodes are inserted directly under the wires that violate antenna rules. But in today's high-density VLSI layouts, there is simply not enough room for "under-the-wire" diode insertion for all wires. Thus, it is necessary to insert many diodes at legal "off-wire" locations and extend the antenna-rule violating wires to connect to their respective diodes. Previously, only simple heuristic algorithms were available for this diode insertion and routing problem. In this paper, we show that the diode insertion and routing problem for an arbitrary given number of routing layers can be optimally solved in polynomial time. Our algorithm guarantees finding a feasible diode insertion and routing solution whenever one exists. Moreover, we can guarantee to find a feasible solution to minimize a cost function of the form α · L + β · N, where L is the total length of extension wires and N is the total number of vias on the extension wires. Experimental results show that our algorithm is very efficient.
KW - Deep submicron
KW - Detailed routing
KW - Layout
KW - Optimization
KW - Very large scale integration (VLSI)
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U2 - 10.1109/TCAD.2003.819888
DO - 10.1109/TCAD.2003.819888
M3 - Article
AN - SCOPUS:0347131040
SN - 0278-0070
VL - 23
SP - 141
EP - 147
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 1
ER -