A polynomial time exact algorithm for self-aligned double patterning layout decomposition

Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D.F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Double patterning lithography (DPL) technologies have become a must for today's sub-32nm technology nodes. There are two leading DPL technologies: self-aligned double patterning (SADP) and litho-etch-litho-etch (LELE). Among these two DPL technologies, SADP has the significant advantage over LELE in its ability to avoid overlay, making it the likely DPL candidate for the next technology node of 14nm. In any DPL technology, layout decomposition is the key problem. While the layout decomposition problem for LELE has been well-studied in the literature, only few attempts have been made to address the SADP layout decomposition problem. In this paper, we present the first polynomial time exact (optimal) algorithm to determine if a given layout has an overlay-free SADP decomposition. All previous exact algorithms were computationally expensive exponential time algorithms based on SAT or ILP. Other previous algorithms for the problem were heuristics without having any guarantee that an overlay-free solution can be found even if one exists.

Original languageEnglish (US)
Title of host publicationISPD'12 - Proceedings of the 2012 International Symposium on Physical Design
Pages17-24
Number of pages8
DOIs
StatePublished - 2012
Event2012 ACM International Symposium on Physical Design, ISPD'12 - Napa, CA, United States
Duration: Mar 25 2012May 28 2012

Publication series

NameProceedings of the International Symposium on Physical Design

Other

Other2012 ACM International Symposium on Physical Design, ISPD'12
Country/TerritoryUnited States
CityNapa, CA
Period3/25/125/28/12

Keywords

  • Layout decomposition
  • Polynomial time algorithm
  • Self-aligned double patterning

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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