A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology

Piotr Dudek, Alexey Lopich, Viktor Gruev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents the design of a vertically-integrated image sensor/processor device, implemented in a fully stacked 3-layer three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. This prototype 'vision chip' contains a 32x32 pixel-parallel processor array. Three silicon layers contain current-mode image sensors, current-mode analogue circuits and digital logic circuits, respectively. The two bottom layers form a mixed-mode cellular processor array, which operates in SIMD mode, and processes the image data acquired by the top-layer backside illuminated photosensor circuit. The intra-processor inter-layer communication is achieved by means of throughsilicon vias, and the system is partitioned to minimise the area overhead associated with this communication. The processor comprises 4 analogue and 12 binary registers, and supports arithmetic and logic operations. Various sensor structures have been implemented to evaluate the efficiency of photo-sensing in SOI technology. The prototype circuit measures 2mmx2mm, with 30μmx30μm pixel pitch. The architecture and circuit design issues are presented in the paper.

Original languageEnglish (US)
Title of host publicationECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
Pages193-196
Number of pages4
DOIs
StatePublished - Dec 10 2009
Externally publishedYes
EventECCTD 2009 - European Conference on Circuit Theory and Design Conference Program - Antalya, Turkey
Duration: Aug 23 2009Aug 27 2009

Publication series

NameECCTD 2009 - European Conference on Circuit Theory and Design Conference Program

Other

OtherECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
CountryTurkey
CityAntalya
Period8/23/098/27/09

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Dudek, P., Lopich, A., & Gruev, V. (2009). A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology. In ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program (pp. 193-196). [5274946] (ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program). https://doi.org/10.1109/ECCTD.2009.5274946