A novel test compression algorithm for analog circuits to decrease production costs

Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression for electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find the minimum for these computationally hard integrals, which corresponds to the optimally compressed analog test. We demonstrate with an op-amp, VCO, and CMOS inverter that the method consistently reduces the length of each test by an average of 93%. Our technology can compress tests in the presence of process variation and utilize parallel processing to speed up the compression algorithm.