A novel test compression algorithm for analog circuits to decrease production costs

Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan

Research output: Contribution to journalArticlepeer-review


Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression for electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find the minimum for these computationally hard integrals, which corresponds to the optimally compressed analog test. We demonstrate with an op-amp, VCO, and CMOS inverter that the method consistently reduces the length of each test by an average of 93%. Our technology can compress tests in the presence of process variation and utilize parallel processing to speed up the compression algorithm.

Original languageEnglish (US)
Pages (from-to)538-548
Number of pages11
JournalIntegration, the VLSI Journal
StatePublished - Jun 2017


  • Analog testing
  • Functional optimization
  • Random tree search
  • Stress testing

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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