A novel low-cost pluggable chip scale package for high pin-count applications

S. W. Crane, James Jeon, Charley Ogata, Ton Wang, Andreas Cangellaris, Jose Schutt-Aine

Research output: Contribution to journalArticlepeer-review


Advances in semiconductor design and fabrication are placing new demands on the engineering community to produce ever more sophisticated package solutions. As the voltage of devices falls, signal integrity issues assume an ever-greater role in the design decision tree. Furthermore, mechanical and thermal challenges often further complicate the designs, for they are moving to finer array sizes and yet increasing wattage. Finally, the semiconductors do not exist as entities unto themselves. They place design and fabrication constraints on the next level of packaging; typically a printed circuit board, already overcrowded and under extreme price pressure. This paper presents an innovative socketable package design that addresses the need for highly integrated packages that offer superior electrical performance at competitive cost. In particular, it is argued that, through careful design of the power and signal distribution through the package, high-density packaging with GHz bandwidth electrical performance is within reach.

Original languageEnglish (US)
Pages (from-to)69-73
Number of pages5
JournalProceedings - Electronic Components and Technology Conference
StatePublished - 2001

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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