A novel low-cost pluggable chip scale package for high-pin-count applications

Jr Crane, J. Jeon, C. Ogata, T. Wang, A. Cangellaris, J. Schutt-Aine

Research output: Contribution to journalConference articlepeer-review


As semiconductor voltages are reduced in order to permit finer feature sizes, and at the same time transistor counts continue to climb, the demands for adequate power and ground become increasingly complex and electrically challenging. There is a growing need for more flexible, even higher-performance electronic packages, yet those factors that have the greatest impact upon the system design, such as I/O counts, bus speeds, serviceability and signal integrity, often conflict directly with traditional packaging approaches. An exploration into alternative methods has produced a new packaging structure called Cluster Grid Array, capable of addressing the need for a pluggable, high-pin-count package with outstanding electrical and mechanical characteristics. This paper provides an overview of the new packaging structure, with emphasis placed on its mechanical and electrical attributes.

Original languageEnglish (US)
Pages (from-to)292-296
Number of pages5
JournalProceedings of SPIE - The International Society for Optical Engineering
StatePublished - 2001
Externally publishedYes
Event2001 HD Interntional Conference on Hig-Density Interconnect and Systems Packaging - Santa Clara, CA, United States
Duration: Apr 17 2001Apr 20 2001

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering


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