A novel half-rate architecture for high-speed clock and data recovery

Keyphrases

• Clock Recovery 100%
• Half-rate 100%
• Phase Detector 50%
• SiGe 25%
• Logic Circuit 25%
• Random Inputs 25%
• Proposed Architecture 25%
• Bang-bang 25%
• Circuit Complexity 25%
• Recovery Circuit 25%
• Full-rate 25%
• Distribution Circuit 25%
• Clock Distribution 25%

Engineering

• Phase Detector 100%
• Simplifies 50%
• Logic Circuit 50%
• Data Rate 50%
• Input Data 50%

Computer Science

• Data Recovery 100%
• Phase Detector 66%
• Circuit Complexity 33%
• Clock Distribution 33%