@inproceedings{af2d57681c594b11bac34216e50de49f,
title = "A novel half-rate architecture for high-speed clock and data recovery",
abstract = "A novel bang-bang half-rate architecture is presented for high-speed random input clock and data recovery. In contrast to the conventional half-rate architectures, which contain two separated full-rate phase detectors and additional complicated logic and clock distribution circuits, the proposed architecture utilizes a genuine half-rate phase detector and eliminates the logic circuits. Therefore, it significantly simplifies the circuit complexity. A SiGe clock and data recovery circuit using this architecture is designed with 40Gb/s input data rate.",
author = "Qiurong He and Milton Feng",
year = "2004",
language = "English (US)",
isbn = "0780384458",
series = "Proceedings - IEEE International SOC Conference",
pages = "351--354",
editor = "J. Chickanosky and D. Ha and R. Auletta",
booktitle = "Proceedings - IEEE International SOC Conference",
note = "Proceedings - IEEE International SOC Conference ; Conference date: 12-09-2004 Through 15-09-2004",
}