A novel half-rate architecture for high-speed clock and data recovery

Qiurong He, Milton Feng

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A novel bang-bang half-rate architecture is presented for high-speed random input clock and data recovery. In contrast to the conventional half-rate architectures, which contain two separated full-rate phase detectors and additional complicated logic and clock distribution circuits, the proposed architecture utilizes a genuine half-rate phase detector and eliminates the logic circuits. Therefore, it significantly simplifies the circuit complexity. A SiGe clock and data recovery circuit using this architecture is designed with 40Gb/s input data rate.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference
EditorsJ. Chickanosky, D. Ha, R. Auletta
Number of pages4
StatePublished - 2004
EventProceedings - IEEE International SOC Conference - Santa Clara, CA, United States
Duration: Sep 12 2004Sep 15 2004

Publication series

NameProceedings - IEEE International SOC Conference


OtherProceedings - IEEE International SOC Conference
Country/TerritoryUnited States
CitySanta Clara, CA

ASJC Scopus subject areas

  • General Engineering


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