A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects

Aosheng Rong, Andreas C Cangellaris, Limin Dong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel graph partitioning technique is proposed for the computationally-efficient and numerically robust implementation of a loop-tree, generalized, partial-element-equivalent-circuit (G-PEEC) modeling of the electromagnetic response of interconnect structures. The proposed technique allows for the identification of loops with controllable profiles and the minimum number of associated branches. The resulting G-PEEC model is successfully applied to the electromagnetic modeling of interconnect structures from almost DC to multiple-tens-of-GHz frequencies.

Original languageEnglish (US)
Title of host publication14th Topical Meeting on Electrical Performance of Electronic Packaging 2005
Pages253-256
Number of pages4
DOIs
StatePublished - Dec 1 2005
Event14th Topical Meeting on Electrical Performance of Electronic Packaging 2005 - Austin, TX, United States
Duration: Oct 24 2005Oct 26 2005

Publication series

NameIEEE Topical Meeting on Electrical Performance of Electronic Packaging
Volume2005

Other

Other14th Topical Meeting on Electrical Performance of Electronic Packaging 2005
Country/TerritoryUnited States
CityAustin, TX
Period10/24/0510/26/05

ASJC Scopus subject areas

  • Engineering(all)

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