A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects

Aosheng Rong; Andreas C. Cangellaris; Limin Dong

doi:10.1109/EPEP.2005.1563751

A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects

Aosheng Rong, Andreas C. Cangellaris, Limin Dong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A novel graph partitioning technique is proposed for the computationally-efficient and numerically robust implementation of a loop-tree, generalized, partial-element-equivalent-circuit (G-PEEC) modeling of the electromagnetic response of interconnect structures. The proposed technique allows for the identification of loops with controllable profiles and the minimum number of associated branches. The resulting G-PEEC model is successfully applied to the electromagnetic modeling of interconnect structures from almost DC to multiple-tens-of-GHz frequencies.

Original language	English (US)
Title of host publication	14th Topical Meeting on Electrical Performance of Electronic Packaging 2005
Pages	253-256
Number of pages	4
DOIs	https://doi.org/10.1109/EPEP.2005.1563751
State	Published - 2005
Event	14th Topical Meeting on Electrical Performance of Electronic Packaging 2005 - Austin, TX, United States Duration: Oct 24 2005 → Oct 26 2005

Publication series

Name	IEEE Topical Meeting on Electrical Performance of Electronic Packaging
Volume	2005

Other

Other	14th Topical Meeting on Electrical Performance of Electronic Packaging 2005
Country/Territory	United States
City	Austin, TX
Period	10/24/05 → 10/26/05

ASJC Scopus subject areas

General Engineering

Online availability

10.1109/EPEP.2005.1563751

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Rong, A., Cangellaris, A. C., & Dong, L. (2005). A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects. In 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005 (pp. 253-256). Article 1563751 (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2005). https://doi.org/10.1109/EPEP.2005.1563751

A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects. / Rong, Aosheng; Cangellaris, Andreas C.; Dong, Limin.
14th Topical Meeting on Electrical Performance of Electronic Packaging 2005. 2005. p. 253-256 1563751 (IEEE Topical Meeting on Electrical Performance of Electronic Packaging; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rong, A, Cangellaris, AC & Dong, L 2005, A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects. in 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005., 1563751, IEEE Topical Meeting on Electrical Performance of Electronic Packaging, vol. 2005, pp. 253-256, 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005, Austin, TX, United States, 10/24/05. https://doi.org/10.1109/EPEP.2005.1563751

Rong A, Cangellaris AC, Dong L. A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects. In 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005. 2005. p. 253-256. 1563751. (IEEE Topical Meeting on Electrical Performance of Electronic Packaging). doi: 10.1109/EPEP.2005.1563751

Rong, Aosheng ; Cangellaris, Andreas C. ; Dong, Limin. / A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects. 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005. 2005. pp. 253-256 (IEEE Topical Meeting on Electrical Performance of Electronic Packaging).

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A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects

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