A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes

Mohammad M. Mansour, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review


A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm 2 programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.

Original languageEnglish (US)
Pages (from-to)371-382
Number of pages12
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Issue number3
StatePublished - Jul 2005


  • LDPC codes
  • Ramanujan graphs
  • Turbo-decoding message-passing algorithm
  • VLSI decoder architectures

ASJC Scopus subject areas

  • Signal Processing
  • Information Systems
  • Electrical and Electronic Engineering


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