A novel and efficient method for power pad placement optimization

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a novel and efficient iterative method for pad placement optimization of power grid with flip chip technology. Power grid with optimized pad placement has less IR-drop values. We develop a new method to calculate new locations of all pads. Placing pads at the new locations reduces local IR-drop values. In order to reduce global IR-drop values, we develop a graph-based strategy to decide which pads are moved to the new locations. After each movement of the pads, a static IR-drop analysis is performed. We develop multigrid accelerated modified Simulated Annealing method (MG-SA) and compare it with the proposed method on a set of test cases. Experimental results show that the proposed method outperforms MG-SA with similar or less IR-drop values and much less runtime.

Original languageEnglish (US)
Title of host publicationProceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013
Pages158-163
Number of pages6
DOIs
StatePublished - 2013
Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA, United States
Duration: Mar 4 2013Mar 6 2013

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other14th International Symposium on Quality Electronic Design, ISQED 2013
Country/TerritoryUnited States
CitySanta Clara, CA
Period3/4/133/6/13

Keywords

  • IR-drop
  • pad placement
  • power grid

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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