A new compact model for external latchup

Farzan Farbiz, Elyse Rosenbaum

Research output: Contribution to journalArticle

Abstract

A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to measurement results from two different technologies, RF-CMOS and SmartMOS.

Original languageEnglish (US)
Pages (from-to)1447-1454
Number of pages8
JournalMicroelectronics Reliability
Volume49
Issue number12
DOIs
StatePublished - Dec 1 2009

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layouts
CMOS
spacing
Electric potential
electric potential
Temperature
temperature

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

A new compact model for external latchup. / Farbiz, Farzan; Rosenbaum, Elyse.

In: Microelectronics Reliability, Vol. 49, No. 12, 01.12.2009, p. 1447-1454.

Research output: Contribution to journalArticle

Farbiz, Farzan ; Rosenbaum, Elyse. / A new compact model for external latchup. In: Microelectronics Reliability. 2009 ; Vol. 49, No. 12. pp. 1447-1454.
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