TY - GEN
T1 - A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chips
AU - Huang, Tsung Wei
AU - Yen, Shih Yuan
AU - Ho, Tsung Yi
PY - 2010
Y1 - 2010
N2 - Electrowetting-on-dielectric (EWOD) chips have emerged as the most widely used actuators for digital microfluidic (DMF) systems. These devices enable the electrical manipulation of microfluidics with various advantages such as low power consumption, flexibility, accuracy, and efficiency. In addressing the need for low-cost and practical fabrication, pin-count reduction has become a key problem to the large-scale integration of EWOD-chip designs. One of the major approaches, broadcast addressing, reduces the pin count by assigning a single control pin to multiple electrodes with mutually compatible control signals. Most previous studies utilize this addressing scheme by scheduling fluidic-level synthesis on pin-constrained chip arrays. However, the associated interconnect routing problem is still not provided in currently available DMF automations, and thus the broadcast-addressing scheme cannot be actually realized. In this paper, we present the first network-flow based pin-count aware routing algorithm for EWOD-chip designs with a broadcast electrode-addressing scheme. Our algorithm simultaneously takes pin-count reduction and wirelength minimization Into consideration for higher integration and better design performance. Experimental results show the effectiveness and scalability of our algorithm on a set of real-life chip applications.
AB - Electrowetting-on-dielectric (EWOD) chips have emerged as the most widely used actuators for digital microfluidic (DMF) systems. These devices enable the electrical manipulation of microfluidics with various advantages such as low power consumption, flexibility, accuracy, and efficiency. In addressing the need for low-cost and practical fabrication, pin-count reduction has become a key problem to the large-scale integration of EWOD-chip designs. One of the major approaches, broadcast addressing, reduces the pin count by assigning a single control pin to multiple electrodes with mutually compatible control signals. Most previous studies utilize this addressing scheme by scheduling fluidic-level synthesis on pin-constrained chip arrays. However, the associated interconnect routing problem is still not provided in currently available DMF automations, and thus the broadcast-addressing scheme cannot be actually realized. In this paper, we present the first network-flow based pin-count aware routing algorithm for EWOD-chip designs with a broadcast electrode-addressing scheme. Our algorithm simultaneously takes pin-count reduction and wirelength minimization Into consideration for higher integration and better design performance. Experimental results show the effectiveness and scalability of our algorithm on a set of real-life chip applications.
UR - http://www.scopus.com/inward/record.url?scp=78650875678&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78650875678&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2010.5653715
DO - 10.1109/ICCAD.2010.5653715
M3 - Conference contribution
AN - SCOPUS:78650875678
SN - 9781424481927
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 425
EP - 431
BT - 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
Y2 - 7 November 2010 through 11 November 2010
ER -