Abstract
Shrinkage of VLSI feature size and use of advanced Reticle Enhancement Technologies (RET) in manufacturing such as OPC and PSM have dramatically pushed up cost of mask. For example of a 130nm or 90nm mask set, the mask cost can easily reach one or two million US dollars. Shuttle mask is an effective method to share the mask cost by putting different chips on the same mask. Shuttle mask floorplanning is a key step to pack these chips according to certain objectives and constraints related to cost, yield, and manufacturability. In this paper, we present a simulated annealing based floorplanner to solve the shuttle mask floorplanning problem with multiple optimization objectives and constraints. We will consider area minimization, density optimization (for manufacturability enhancement with CMP), wafer utilization maximization, die-to-die inspection constraint, die orientation constraint and their combinations. A nice property of our floorplanner is that it can be easily adapted to different cost models of mask and wafer manufacturing. Experiments on industry data show promising results.
| Original language | English (US) |
|---|---|
| Article number | 38 |
| Pages (from-to) | 340-350 |
| Number of pages | 11 |
| Journal | Proceedings of SPIE - The International Society for Optical Engineering |
| Volume | 5567 |
| Issue number | PART 1 |
| DOIs | |
| State | Published - Dec 1 2004 |
| Event | 24th Annual BACUS Symposium on Photomask Technology - Monterey, CA, United States Duration: Sep 14 2004 → Sep 17 2004 |
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Keywords
- Floorplanning
- Multi-objective
- Shuttle mask
- Simulated annealing
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering
Cite this
A multi-objective floorplanner for shuttle mask optimization. / Xu, Gang; Tian, Ruiqi; Pan, David Z.; Wong, Martin D.F.
In: Proceedings of SPIE - The International Society for Optical Engineering, Vol. 5567, No. PART 1, 38, 01.12.2004, p. 340-350.Research output: Contribution to journal › Conference article
}
TY - JOUR
T1 - A multi-objective floorplanner for shuttle mask optimization
AU - Xu, Gang
AU - Tian, Ruiqi
AU - Pan, David Z.
AU - Wong, Martin D.F.
PY - 2004/12/1
Y1 - 2004/12/1
N2 - Shrinkage of VLSI feature size and use of advanced Reticle Enhancement Technologies (RET) in manufacturing such as OPC and PSM have dramatically pushed up cost of mask. For example of a 130nm or 90nm mask set, the mask cost can easily reach one or two million US dollars. Shuttle mask is an effective method to share the mask cost by putting different chips on the same mask. Shuttle mask floorplanning is a key step to pack these chips according to certain objectives and constraints related to cost, yield, and manufacturability. In this paper, we present a simulated annealing based floorplanner to solve the shuttle mask floorplanning problem with multiple optimization objectives and constraints. We will consider area minimization, density optimization (for manufacturability enhancement with CMP), wafer utilization maximization, die-to-die inspection constraint, die orientation constraint and their combinations. A nice property of our floorplanner is that it can be easily adapted to different cost models of mask and wafer manufacturing. Experiments on industry data show promising results.
AB - Shrinkage of VLSI feature size and use of advanced Reticle Enhancement Technologies (RET) in manufacturing such as OPC and PSM have dramatically pushed up cost of mask. For example of a 130nm or 90nm mask set, the mask cost can easily reach one or two million US dollars. Shuttle mask is an effective method to share the mask cost by putting different chips on the same mask. Shuttle mask floorplanning is a key step to pack these chips according to certain objectives and constraints related to cost, yield, and manufacturability. In this paper, we present a simulated annealing based floorplanner to solve the shuttle mask floorplanning problem with multiple optimization objectives and constraints. We will consider area minimization, density optimization (for manufacturability enhancement with CMP), wafer utilization maximization, die-to-die inspection constraint, die orientation constraint and their combinations. A nice property of our floorplanner is that it can be easily adapted to different cost models of mask and wafer manufacturing. Experiments on industry data show promising results.
KW - Floorplanning
KW - Multi-objective
KW - Shuttle mask
KW - Simulated annealing
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U2 - 10.1117/12.569345
DO - 10.1117/12.569345
M3 - Conference article
AN - SCOPUS:19844362715
VL - 5567
SP - 340
EP - 350
JO - Proceedings of SPIE - The International Society for Optical Engineering
JF - Proceedings of SPIE - The International Society for Optical Engineering
SN - 0277-786X
IS - PART 1
M1 - 38
ER -