A Monte Carlo simulation environment for wear out in VLSI systems

G. S. Choi, Ravishankar K Iyer, J. H. Patel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switching activity is collected. This data is then used along with Monte Carlo simulation to model wear-out at the chip-level.

Original languageEnglish (US)
Title of host publicationVLSI Design 1991 - Digest of Papers - 4th CSI/IEEE International Symposium on VLSI Design
PublisherIEEE Computer Society
Pages249-254
Number of pages6
ISBN (Electronic)0818621257
DOIs
StatePublished - Jan 1 1991
Event4th CSI/IEEE International Symposium on VLSI Design, VLSI 1991 - New Delhi, India
Duration: Jan 4 1991Jan 8 1991

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Conference

Conference4th CSI/IEEE International Symposium on VLSI Design, VLSI 1991
CountryIndia
CityNew Delhi
Period1/4/911/8/91

Keywords

  • Reliability prediction
  • VLSI
  • device failure mechanism
  • electromigration
  • simulation
  • time-to-failure

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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