A mechanism for logic upset induced by power-on ESD

Yang Xiu, Nicholas Thomson, Robert Mertens, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2014
PublisherESD Association
EditionNovember
ISBN (Electronic)1585372587, 9781585372577
StatePublished - Nov 26 2014
Event36th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2014 - Tucson, United States
Duration: Sep 7 2014Sep 12 2014

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
NumberNovember
Volume2014-November
ISSN (Print)0739-5159

Other

Other36th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2014
Country/TerritoryUnited States
CityTucson
Period9/7/149/12/14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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