A mechanism for logic upset induced by power-on ESD

Yang Xiu; Nicholas Thomson; Robert Mertens; Elyse Rosenbaum

A mechanism for logic upset induced by power-on ESD

Yang Xiu, Nicholas Thomson, Robert Mertens, Elyse Rosenbaum

Research output: Contribution to journal › Conference article › peer-review

Abstract

Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.

Original language	English (US)
Journal	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume	2014-November
Issue number	November
State	Published - Nov 26 2014
Event	36th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2014 - Tucson, United States Duration: Sep 7 2014 → Sep 12 2014

ASJC Scopus subject areas

Electrical and Electronic Engineering

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title = "A mechanism for logic upset induced by power-on ESD",

abstract = "Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.",

author = "Yang Xiu and Nicholas Thomson and Robert Mertens and Elyse Rosenbaum",

year = "2014",

month = nov,

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language = "English (US)",

volume = "2014-November",

journal = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings",

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T1 - A mechanism for logic upset induced by power-on ESD

AU - Xiu, Yang

AU - Thomson, Nicholas

AU - Mertens, Robert

AU - Rosenbaum, Elyse

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Y1 - 2014/11/26

N2 - Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.

AB - Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.

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M3 - Conference article

AN - SCOPUS:84938151184

SN - 0739-5159

VL - 2014-November

JO - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

JF - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

IS - November

T2 - 36th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2014

Y2 - 7 September 2014 through 12 September 2014

ER -

A mechanism for logic upset induced by power-on ESD

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