Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.
|Original language||English (US)|
|Journal||Electrical Overstress/Electrostatic Discharge Symposium Proceedings|
|State||Published - Nov 26 2014|
|Event||36th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2014 - Tucson, United States|
Duration: Sep 7 2014 → Sep 12 2014
ASJC Scopus subject areas
- Electrical and Electronic Engineering