A mechanism for logic upset induced by power-on ESD

Yang Xiu, Nicholas Thomson, Robert Mertens, Elyse Rosenbaum

Research output: Contribution to journalConference article

Abstract

Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.

Original languageEnglish (US)
JournalElectrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume2014-November
Issue numberNovember
StatePublished - Nov 26 2014
Event36th International Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2014 - Tucson, United States
Duration: Sep 7 2014Sep 12 2014

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Transistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A mechanism for logic upset induced by power-on ESD. / Xiu, Yang; Thomson, Nicholas; Mertens, Robert; Rosenbaum, Elyse.

In: Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Vol. 2014-November, No. November, 26.11.2014.

Research output: Contribution to journalConference article

Xiu, Yang ; Thomson, Nicholas ; Mertens, Robert ; Rosenbaum, Elyse. / A mechanism for logic upset induced by power-on ESD. In: Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 2014 ; Vol. 2014-November, No. November.
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